Resilient Soft-Error Endurable Latch Design
J.Sofia Priya Dharshini1, B. Sirisha2
1Dr.J.Sofia Priya Dharshini, Dept. of ECE, RGMCET, Nandyal, Andhra Pradesh, India.
2Mrs. B. Shirisha, Dept. of ECE, RGMCET, Nandyal, (Andhra Pradesh), India.
Manuscript received on July 20, 2019. | Revised Manuscript received on August 10, 2019. | Manuscript published on August 30, 2019. | PP: 759-768 | Volume-8 Issue-6, August 2019. | Retrieval Number: F7991088619/2019©BEIESP | DOI: 10.35940/ijeat.F7991.088619
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Errors may occur in the circuit output because of upset in the stored or communicated charge. Such errors are considered as Transient Faults. The Transient Fault (TF) causes the soft error in the circuit output. So, designing of the latches which are unsusceptible to the Transient Faults disregarding the hitting particles energy is proposed in this project. Traditionally the soft-error based VLSI is limited to applications which require high reliability and operated in high radiation environment such as avionics applications, medical equipments, space industry and military applications. However, CMOS technology scales down to nanometre region, VLSI circuits also get affected by soft errors at ground level which features low radiation energy. Here, in this paper, totally three soft error tolerant latch designs are proposed, which includes High Performance, low cost and resilient soft error endurable latch, HLR-CG, HLR-CG1 and modified HLR-CG1. The proposed designs achieve better reliability with lower power consumption, delay, power delay product and area. The latches proposed are implemented in 45 nm technology and 32 nm technologies.
Keywords: Transient Fault, Soft Error, radiation hardening, reliability.