FPGA Based Optimized Reconfigurable Base-2 Constant Coefficient Multiplier Architecture for Image Filtering
N. Sambamurthy1, M. Kamaraju2
1N. Sambamurthy, Department of ECE, Gudlavalleru Engineering College, Gudlavalleru, India.
2Dr. M. Kamaraju, Department of ECE, Gudlavalleru Engineering College, Gudlavalleru, India
Manuscript received on 15 September 2019 | Revised Manuscript received on 24 September 2019 | Manuscript Published on 10 October 2019 | PP: 822-825 | Volume-8 Issue-6S2, August 2019 | Retrieval Number: F12060886S219/19©BEIESP | DOI: 10.35940/ijeat.F1206.0886S219
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Image convolution using FPGA has been comprehensively used for noise removal of Reconfigurable computing based image Processing Algorithm. Particularly these filters are widely used in embedded computer vision applications like edge detection and Feature extraction analysis. Practical implementation of filter requires enormous computational requirement. The multiplier plays very important role in the image convolution. The existed multiplier design requires more computational complexity for the 3×3 test image. For this the proposed reconfigurable constant coefficient multiplier uses base-2 Common sub expression algorithm. which reduces the computational complexity in a better way. The proposed 2D-convolution in image application is the value of resultant output is multiplication of image pixel with corresponding kernel value. In this work the realization of 2D convolution to be done using proposed constant coefficient multiplier and analyzed using Xilinx Virtex-5 FPGA platform.
Keywords: Field Programmable Gate Array (Fpgas), Filters, 2D Filters, Gaussian Mask; BCSE, Mask, Image Controller.
Scope of the Article: FPGAs