Subthreshold Region based Linear Feedback Shift Register
B. Lakshmi1, M. Kamaraju2, K.Babulu3
1B. Lakshmi, Research Scholor, JNTUK & Assistant Professor, Department of ECE, G V P College of Engineering Women, Visakhapatnam (A.P), India.
2Dr. M. Kamaraju, Professor, Department of ECE, Gudlavalleru Engineering College, Gudlavalleru, India.
3Dr. K. Babulu, Professor, Department of ECE, JNTUK, Kakinada (A.P), India.
Manuscript received on 15 September 2019 | Revised Manuscript received on 24 September 2019 | Manuscript Published on 10 October 2019 | PP: 817-821 | Volume-8 Issue-6S2, August 2019 | Retrieval Number: F12050886S219/19©BEIESP | DOI: 10.35940/ijeat.F1205.0886S219
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Abstract: Growing demand for portable devices and fast increases in complexity of chip cause power dissipation is an important parameter. Power consumption and dissipation or generations of more heat possess a restriction in the direction of the integration of more transistors. Several methods have been proposed to reduce power dissipation from system level to device level. Subthreshold circuits are widely used in more advanced applications due to ultra low-power consumption. The present work targets on construction of linear feedback shift registers (LFSR) in weak inversion region and their performance observed in terms of parameters like power delay product (PDP). In CMOS circuits subthreshold region of operation allows a low-power for ample utilizations but this advantage get with the penalty of flat speed. For the entrenched and high speed applications, improving the speed of subthreshold designs is essential. To enhance this, operate the devices at maximum current over capacitance. LFSR architectures build with various types of D flip flop and XOR gate circuits are analyzed. Circuit level Simulation is carried out using 130 nm technologies.
Keywords: Subthreshold Region, Superthreshold Region LFSR; Low Power, DIBL, INWE.
Scope of the Article: Low-power design