22nm PTM Model Low Power yet High Speed CMOS High K Metal Gate Strained Silicon Technology Inverter
Shobha Sharma
Shobha sharma, ECE Dept, Indira Gandhi Institute of Technology, GGSIP university, Delhi, India.
Manuscript received on April 05, 2012. | Revised Manuscript received on may 23, 2012. | Manuscript published on June 30, 2012. | PP: 87-90 | Volume-1 Issue-5, June 2012 | Retrieval Number: E0446051512/2012©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: This paper analysis four inverter configuration with low power and high performance PTM models of Arizona State University, USA at 22nm technology with High K metal gate strained silicon technology. The effect of stacked transistor is analysed to show the reduced average and peak power dissipation. This stack effect is utilized in combination with forward biasing of a transistor to have low power but high speed inverter without loosing the maximum and minimum voltage swing at the output. Average power dissipated by low power stacked forward biased inverter is reduced by 4% compared to HP inverter. Peak power reduction is 64% in case of this new inverter compared to traditional High Performance inverter. The propagation delay is more compared to a HP inverter but is reduced by almost 18.2% compared to Low Power stacked inverter. 
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