A Leakage Power Aware Transmission Gate Level Shifter
Srinivasulu Gundala

Srinivasulu Gundala, Department of Electronics and Communication Engineering, Lakireddy Bali Reddy College of Engineering, Vijayawada (A.P), India
Manuscript received on 18 April 2019 | Revised Manuscript received on 25 April 2019 | Manuscript published on 30 April 2019 | PP: 1527-1530 | Volume-8 Issue-4, April 2019 | Retrieval Number: D6428048419/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: The clustered voltage scaling systems are ultimate power reduction techniques, uses voltage level shifters (LSs) to interface multi voltage domains to reduce power at system level. The LS may become overhead when its own power consumption and delay is high. In this paper we presented a new schematic of level shifter with single supply voltage to perform voltage level shift, which uses Transmission gate based circuit topology. The simulation results says it has energy per transition is 1.80E-14 J at 1 MHz frequency and the level shifter delay is 2.6 ns at VDDL 0.3V and VDDH 1V. The design has simulated by using 90nm CMOS technology files. This new architecture is more efficient then existing architectures.
Keywords: Delay, Level Shifter, New Architecture, Power Consumption, Transmission Gate.

Scope of the Article: Wireless Power Transmission