Efficient Timing Recovery Technique for Software Defined Radio Receiver using FPGA
Sabah SHehd Abdulabas
Sabah SHehd Abdulabas, Department of Electronic Technology, Institute of Technology, Baghdad-Iraq.
Manuscript received on March 20, 2014. | Revised Manuscript received on April 09, 2014. | Manuscript published on April 30, 2014. | PP: 278-286  | Volume-3, Issue-4, April 2014. | Retrieval Number:  D2924043414/2013©BEIESP

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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: This paper presents the timing recovery in software defined radio receiver as a widely used technique nowadays. Software defined radios (SDR) is the more configurable hardware platforms that provide the technology for realizing the fast growing third and new generation digital wireless communication structure. The more complex duty performed in a high data rate wireless system is the synchronization. The timing synchronization in SDRs using FPGA based signal processors is introduced. The 16-QAM loop for performing coherent demodulation were described and reported on the suggestion of FPGA automation. A matched filter control system is used to provide and addressed the symbol timing recovery technique. To explain the operations of the timing recovery loop and reflection, much approach is adopted and outlined for FPGA performance.
Keywords: Timing Recovery, SDR, FPGA.