An Efficiednt Programmable Frequency Divider with Improved Division Ratio
N. Kirthika1, Nisha Lali R.2, Rejeesh R. S.3
1N. Kirthika, Asst. Professor – M.E.Vlsi Desing, Sri Ramakrishna Engineering College, Coimbatore, Tamilnadu, India.
2Nisha Lali R., PG Scholar-Dept. of Electronics and Communication Engg, TKM Institute of Technology, Kollam, Kerala, India.
3Rejeesh R. S., PG Scholar – M.E. Vlsi Desing, Sri Ramakrishna Engineering College, Coimbatore, Tamilnadu, India.
Manuscript received on March 01, 2012. | Revised Manuscript received on March 25, 2012. | Manuscript published on April 30, 2012. | PP: 69-72 | Volume-1 Issue-4, April 2012 | Retrieval Number: D0257031412/2012©BEIESP

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Abstract: The frequency divider is an important building block in today’s high speed integrated circuits. Frequency divider is the most power hungry block in the communication system. Considering the scope of the frequency divider An Efficient Programmable Frequency Divider (PD) is presented. In this paper a shared counter with a small control circuit is exploited using Reduced Module Control Signal generator (RMCS).This will reduce the output load capacitance and the redundant counter operations in the divider. A Dual Modules Prescaler (DMP), which gives initial division ratio for the input signal by N or N+1.Dividing factor of the Efficient PD can increased by modifying DMP circuit for 16 or 17. A novel glitch less D flip-flop is also designed by considering the switching activities of the internal nodes of the flip-flop.
Keywords: Dual modulus prescaler (DMP), programmable divider (PD), Reduced module control signal generator (RMCS).