CMOS Circuit Design for Classification of ST and VT Arrhythmia Based on Morphological Analysis using Neural Network Classifier
D. Hari Priya1, D. Ravali2
1Dr. D. Hari Priya, Associate Professor, Department of Electronics and Communication Engineering, Anurag Group of Institutions, Hyderabad, India.
2D. Ravali, M.Tech, Department of Electronics and Communication Engineering, Anurag Group of Institutions, Hyderabad, India.
Manuscript received on February 06, 2020. | Revised Manuscript received on February 10, 2020. | Manuscript published on February 30, 2020. | PP: 1283-1287 | Volume-9 Issue-3, February, 2020. | Retrieval Number: B4114129219/2020©BEIESP | DOI: 10.35940/ijeat.B4114.029320
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Ventricular tachycardia is a life threatening medical emergency. Discerning dangerous ventricular rhythms with safe Sinus tachycardia based on heart rate is very tough as they are having similar heart rate. Most of the existing research used time information for classification which may lead false alarm. Hence a CMOS circuit is proposed to classify ventricular-tachycardia based on morphological changes in QRS complex. The design includes sample and hold circuit for sampling QRS complex, mapping circuit for map the given input signal to unit length, hamming neural network and winner take all circuits for classification of ventricular tachycardia. This design is implemented using 180nm CMOS technology with the operating voltage and power consumption of 19.81µW.
Keywords: Sinus tachycardia, Ventricular tachycardia, arrhythmia classifier, Hamming Neural Network, WTA Networks.