Convolutional encoder, FPGA, Register Exchange, Spartan XC3S400A Board, Viterbi decode Distributed Routing Simulation for Generic Network-on-Chip Topologies
Naveen Choudhary, Department of Computer Science and Engineering, College of Technology and Engineering, Maharana Pratap University of Agriculture and Technology, Udaipur, Rajasthan, India.
Manuscript received on October 06, 2011. Revised Manuscript received on October 12, 2011. Manuscript published on October 30, 2011 . | PP: 90-95 | Volume-1 Issue-1, October 2011. | Retrieval Number: A0120101111/2011©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Networks-on-Chip (NoC) is recently proposed as an alternative to the on-chip bus to meet the increasing requirement of complex communication needs in Systems-on-Chip (SoC). Most researchers advocate the use of traditional regular networks like meshes as architectural templates which gained a high popularity in general-purpose parallel computing. However, most SoC platforms are special-purpose tailored to the domain-specific requirements of their application. They are usually built from a large diversity of heterogeneous components which communicate in a very specific, mostly irregular way. In such systems the size and nature of cores may vary quite widely making the topology irregular. Moreover regular topologies can become irregular due to faults in links and switches. In such scenario topology agnostic routing algorithms are generally required. In this paper, we have analyzed the performance and applicability distributed table based routing for irregular NoC on an Network-on-Chip simulation framework.
Keywords: Distributed routing, Interconnection networks, NoC, SoC.