FPGA Based Efficient Implementation of Viterbi Decoder
Anubhuti Khare1, Manish Saxena2, Jagdish Patel3
Dr. Anubhuti Khare, Reader,Department of Electronics and Communication, University Institute of Technology, Rajeev Gandhi Technical University, Bhopal, (MP), India.
2Manish Saxena, Head of Electronics and Communication Department, Bansal Institute Of Science and Technology, Bhopal, (MP), India.
3Jagdish Patel, M.Tech (Digital Comm), Bansal Institute of Science and Technology, Bhopal, (MP), India.
Manuscript received on October 06, 2011. | Revised Manuscript received on October 12, 2011. | Manuscript published on October 30, 2011. | PP: 84-89 | Volume-1 Issue-1, October 2011. | Retrieval Number: A0118101111/2011©BEIESP
Open Access | Ethics and  Policies | Cite
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: It is well known that data transmissions over wireless channels are affected by attenuation, distortion, interference and noise, which affect the receiver’s ability to receive correct information. Convolutional encoding with Viterbi decoding is a powerful method for forward error detection and correction. It has been widely deployed in many wireless communication systems to improve the limited capacity of the communication channels. In this paper, we present a Spartan XC3S400A Field-Programmable Gate Array efficient implementation of Viterbi Decoder with a constraint length of 3 and a code rate of 1/3. The Viterbi Decoder is compatible with many common standards, such as DVB, 3GPP2, 3GPP LTE, IEEE 802.16, Hiperlan, and Intelsat IESS-308/309.
Keywords: Convolutional encoder, FPGA, Register Exchange, Spartan XC3S400A Board, Viterbi decoder.