Designing & FPGA Implementation of IIR Filter Used for Detecting Clinical Information from ECG
Manish Kansal1, Hardeep Singh Saini2, Dinesh Arora3
Manish Kansal, Department of Electronics & Communication Engineering, Panchkula Engineering College, Barwala Kurukshetra University, Kurukshetra, India.
2Hardeep Singh Saini, Department of Electronics & Communication Engineering, Indo Global College, Abhipur,, India.
3Dinesh Arora, Department of Electronics & Communication Engineering, SDDIET Barwala, India.
Manuscript received on October 06, 2011. | Revised Manuscript received on October 12, 2011. | Manuscript published on October 30, 2011 . | PP: 67-72 | Volume-1 Issue-1, October 2011. | Retrieval Number: A0115101111/2011©BEIESP
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Abstract: This paper describes an approach to design and implementation of digital filter algorthims based on field programmable gate arrays (FPGAs).The advantages of FPGA approach to digital filter implementation include higher sampling rates than are available from traditional DSP chips, lower cost than ASIC for moderate volume applications An ECG is a simple and useful test which records the rhythm and electrical activity of the heart of the patient that suffers from any heart disease While recording ECG signal it gets corrupted due to different noise interferences and artefacts. Noise and interference are usually large enough to obscure small amplitude features of the ECG hat are of physiological or clinical interest. The bandwidth of the noise overlaps that of wanted signals, so that simple filtering cannot sufficiently enhance the signal to noise ratio…We have used MATLAB for this purpose as it is the most advanced tool for DSP applications. Also it helps to verify the design and results that comes from the hardware.
Keywords: FIR, IIR, FPGA,Mat lab, VHDL