High Speed, Low Area Exact Speculative Carry Look Ahead Adder using MGDI Technique
K. Lakshmi Bhanu Prakash Reddy1, S.Vijayakumar2, P.Umasankar3, G. Reddy Hemantha4

1K. Lakshmi Bhanu Prakash Reddy, Department of ECE, Aditya College of Engineering, Madanapalle, Andhra Pradesh, India.
2S.Vijayakumar, Department of ECE, SITAMS-Autonomous, Chittoor, Andhra Pradesh, India.
3P.Umasankar, Department of EEE, Mahendra Engineering College, Autonomous, Namakkal, Tamil Nadu, India
4G. Reddy Hemantha, 1,4Research Scholar, Jawaharlal Nehru Technological University, Anantapuramu, India.
Manuscript received on July 20, 2019. | Revised Manuscript received on August 10, 2019. | Manuscript published on August 30, 2019. | PP: 5090-5094 | Volume-8 Issue-6, August 2019. | Retrieval Number: F9557088619/2019©BEIESP | DOI: 10.35940/ijeat.F9557.088619
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: The Exact Speculative Carry Look Ahead Adder using the Modified-GDI (Modified-Gate Diffusion Input) is suggested in this work. The delay, area and power tradeoff plays a vital role in VLSI. We already know that designs which are of CMOS style occupy more space may consume more power consumption. The switching behavior of the circuit cause the heating up of integrated circuits affects the working conditions of the functional unit. The adders are the main parts of several applications such as microprocessors, microcontrollers and digital signal processors and also in real time applications. Hence it is important to minimize the adder blocks to design a perfect processor. This work is proposed on a 16 bit carry look ahead adder is designed by using MGDI gate and 4T XOR gates and a speculator blocks. The proposed MGDI carry Look Ahead adder occupies 68% less area and the power consumption and the propagation delay also drastically reduces when compared to the conventional carry Look Ahead adder why because the number transistors drastically reduces from 1448 (Conventional) to 456 (Proposed CLA). The simulation results of the proposed design implemented in Xilinx.
Keywords: MGDI; 4T XOR; CLA; Speculator; Area; Power Consumption; VLSI; ASIC.