Clock Tree Optimization for Multi-Corner Multi-Mode Timing Closure with Different Design Flows
Kasi Annapurna.Nalluri1, G. R. L.V. N. Srinivasa Raju2
1Kasi Annapurna.Nalluri, Physical Design Engineer in a reputed company on lower node technologies from APR (Automatic Place and Route) to Sign-Off (GDSOUT).
2G. R. L.V. N. Srinivasa Raju, Professor and HOD in the Department of ECE, Shri Vishnu Engineering College for Women, Bhimavaram.
Manuscript received on July 30, 2019. | Revised Manuscript received on August 25, 2019. | Manuscript published on August 30, 2019. | PP: 4316-4324 | Volume-8 Issue-6, August 2019. | Retrieval Number: F8924088619/2019©BEIESP | DOI: 10.35940/ijeat.F8924.088619
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Abstract: Clock Tree Optimization for Multi Corner Multi Mode Timing closure is done with Integrated Clock Gating cells. It is power efficient clock tree technique because, it will reduce the switching power usage of clock. It is implemented using integrated clock Gating cells for reducing the switching power caused by clock propagation in the design during Clock Tree Synthesis. The multi mode and multi corner uses integrated clock gating cells to achieve timing and these cells will reduce dynamic power .This technique can be applied to industrial Digital Intellectual Property(DIP). The cells used in the design are fabricated by using 22nm FDSOI process and these cells used as clock pins by Automatic Root Clock Pin (ARCP) in Clock Specification file during clock tree synthesis along with proposed flows for reducing buffer count. The result shows that the number of buffers added in the each stage is reduced by the proposed flow and also we achieve the timing, power and area. In this paper, by using clock tree optimization technique the clock power dissipation in the chip is reduced by Integrated clock gating cells. 
Keywords: ARCP (Automatic Root Clock Pin) ,Clock Gating (CG), Clock Tree synthesis, ECO (Engineering Change Order), FDSOI (Fully Depleted Silicon On Insulator) , Macro Model, MCMM (Multi Corner and Multi Mode).