A Variable Processor Cache Line Size Architecture
S Subha,, Department of IT and Engineering, SITE, Vellore Institute of Technology, Vellore, (Tamil Nadu), India.
Manuscript received on July 20, 2019. | Revised Manuscript received on August 10, 2019. | Manuscript published on August 30, 2019. | PP: 1724-1727 | Volume-8 Issue-6, August 2019. | Retrieval Number: F8427088619/2019©BEIESP | DOI: 10.35940/ijeat.F8427.088619
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Processor caches have fixed line size. A processor cache defined by tuple (C, k, L) where C is the capacity, k associativity and L line size has fixed values for the parameters. Algorithms to have variable processor cache line size are proposed in literature. This paper proposes algorithm to have variable cache line size based on the miss count for any application. The line size is varied by increasing or decreasing line size based on the miss count for any time interval. The algorithm can be used in running any application. The SPEC2000 benchmarks are used for simulating the proposed algorithm for cache with one level. The average memory access time is chosen as performance parameter. A performance improvement of 12% is observed with energy saving of 18% for chosen parameters.
Keywords: Average Memory Access Time, Cache line size, Energy, Set associative cache.