A 9-Bit, 200MS/s Low Power CMOS Pipeline ADC
Manju Devi1, Arun Kumar P. Chavan2, K. N. Muralidhara3
1Manju Devi, Department of Electronics and Communication, Visvesvaraya Technological University (VTU), Karnataka, India.
2Arun Kumar P. Chavan, Department of Electronics and Communication, Visvesvaraya Technological University (VTU), Karnataka, India.
3Dr. K. N. Muralidhara, Department of Electronics and Communication, College of Engineering, Mandya, India.
Manuscript received on July 27, 2014. | Revised Manuscript received on August 02, 2014. | Manuscript published on August 30, 2014. | PP: 180-183  | Volume-3 Issue-6, August 2014.  | Retrieval Number:  F3372083614/2013©BEIESP

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Abstract: This paper describes 9-bit, 200MS/s Pipeline analog to digital converter implemented in 0.18µm CMOS process consuming 48.97mW power from 1.8v supply. To improve the linearity of pipeline ADC is designed which has three stages, 3-bit, stage architecture. Operational transcconductance amplifier is adopted in all pipeline stage to give good power efficiency. The converter is optimized for low voltage, low power application by optimizing opamp and 3- bit flash at circuit level.
Keywords: Operational Transconductance Amplifier (OTA), Thermometric Codes, Flash ADC, Pipeline ADC.