Multilevel Inverter Topology with Reduced Number of Switches
K. Esakkishenbaga Loga1, SP. Umayal2
1K. Esakkishenbaga Loga, Research Scholar, Anna University, Chennai (Tamil Nadu), India.
2S P. Umayal, Professor, PSN College of Engineering and Technology, Tirunelveli (Tamil Nadu), India.
Manuscript received on 30 September 2019 | Revised Manuscript received on 12 November 2019 | Manuscript Published on 22 November 2019 | PP: 1730-1733 | Volume-8 Issue-6S3 September 2019 | Retrieval Number: F13250986S319/19©BEIESP | DOI: 10.35940/ijeat.F1325.0986S319
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Abstract: The commencement of multilevel inverter has enamored the researchers owing to its applications for medium and high power. Moreover there has consistently been a necessity for an approach with reduced number of switches. Bearing this in mind, this article presents an asymmetrical multilevel inverter with a switching approach employing reduced number of power electronics equipments. The increase in the level of output, number of switching equipments besides with the switching states enhances. As a consequence, higher switching losses occurs that prompts power loss. Accordingly, the efficiency of the complete conversion network diminishes. The significant characteristics of this submitted work is that the module can be accomplished as sub multiple level assembly. Progressively, with minimal rise in the switching elements, all number of levels can be elongated.
Keywords: Multi-level Inverter, Symmetrical & Asymmetrical MLI, THD (Total Harmonic Distortion), Simulation.
Scope of the Article: Network Modelling and Simulation