Design of Dadda and Wallace Tree Multiplier Using Compressor Technique
S N Shivappriya M1, Narmatha2, V. Madhusri3
1Dr. S N Shivappriya M, Kumaraguru College of Technology, Coimbatore (Tamil Nadu), India.
2Narmatha, Kumaraguru College of Technology, Coimbatore (Tamil Nadu), India.
3V. Madhusri, Kumaraguru College of Technology, Coimbatore (Tamil Nadu), India.
Manuscript received on 30 September 2019 | Revised Manuscript received on 12 November 2019 | Manuscript Published on 22 November 2019 | PP: 1551-1554 | Volume-8 Issue-6S3 September 2019 | Retrieval Number: F12800986S319/19©BEIESP | DOI: 10.35940/ijeat.F1280.0986S319
Open Access | Editorial and Publishing Policies | Cite | Mendeley | Indexing and Abstracting
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (

Abstract: The work portrays about the design of the Dadda multiplier using 4:2 compressor techniques. The three design techniques, namely conventional design, optimized design using exclusive OR with multiplexer and a further optimized design with less number of critical paths with gates are implemented. All the three designs are implemented in Dadda multiplier and wallace tree multiplier and their performances are compared. The performance metrics measured are area, power consumption, delay and transistor count and these parameters are efficient in dadda multiplier compared to wallace tree multiplier with the above three design techniques. The designs are using behavioral modeling and the results are taken in the 180nm Cadence tool. The result shows that the Dadda multiplier performs better in terms of delay, area and transistor count for all three designs than the Wallace tree multiplier.
Keywords: Compressor Technique, Dadda Multiplier, Wallace Tree Multiplier, Area, Delay, Transistor Count.
Scope of the Article: Low-power design