Stacking Technique for Low Power Sram
Karthik B1, Jasmin M2, Arulselvi S3
1Karthik B, Assistant Professor, Department of Electronics and Communication Engineering, Bharath Institute of Higher Education and Research, Chennai (Tamil Nadu), India.
2Jasmin M, Assistant Professor, Department of Electronics and Communication Engineering, Bharath Institute of Higher Education and Research, Chennai (Tamil Nadu), India.
3Arulselvi S, Assistant Professor, Department of Electronics and Communication Engineering, Bharath Institute of Higher Education and Research, Chennai (Tamil Nadu), India.
Manuscript received on 13 September 2019 | Revised Manuscript received on 22 September 2019 | Manuscript Published on 10 October 2019 | PP: 118-121 | Volume-8 Issue-6S2 August 2019 | Retrieval Number: F10950886S219/19©BEIESP | DOI: 10.35940/ijeat.F1095.0886S219
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Static random access memory leakage current is becoming one of the critical issues for low-power systems. SRAM-based FinFET Double Gate has become a better option for profound submicron techniques owing to its better short channel effect. In this work, we review some of the leakage current sources and low power reduction technique to reduce leakage. As animprovement of our research work,6T SRAM memory cells can be implemented using independent gate FinFET which gives lower leakage as well as better performance over the shorted gate FinFET mode. This is also implemented using stacking technique to decrease leakage. Therefore, the power devoured by the different SRAM cells is likened with the Tanner tool in 45 nm technique.
Keywords: Finfets, High-Performance, Short Channel Effects (Sces), Low Power (LP) Mode, Independent Gate (IG) Mode, Shorted Gate (SG) Mode.
Scope of the Article: Low-power design