Design and Implementation of OFDM (Orthogonal Frequency Division Multiplexing) using VHDL and FPGA
Manjunath Lakkannavar1, Ashwini Desai2
1Manjunath Lakkannavar, Electronics and Communication Engineering, Visvesvaraya Technological University/ VTU Extension Centre, UTL Technologies Limited, Bangalore, India.
2Ashwini Desai, Electronics and Communication Engineering, Visvesvaraya Technological University / KLESCET, Belgaum, India.
Manuscript received on July 17, 2012. | Revised Manuscript received on August 25, 2012. | Manuscript published on August 30, 2012. | PP: 211-213 | Volume-1 Issue-6, August 2012.  | Retrieval Number: F0668081612/2012©BEIESP

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Abstract: Orthogonal Frequency Division Multiplexing (OFDM) is a multi carrier modulation technique which divides the available spectrum into many carriers. OFDM uses the spectrum efficiently compared to FDMA by spacing the channels much closer together and making all carriers orthogonal to one another to prevent interference between the closely spaced carriers. OFDM provides high bandwidth efficiency because the carriers are orthogonal to each others and multiple carriers share the data among themselves. The main advantage of this transmission technique is their robustness to channel fading in wireless communication environment. The main objective of this project is to design and implement a base band OFDM transmitter and receiver using FPGA. This project focuses on the core processing block of an OFDM system, which are the Fast Fourier Transform (FFT) block and the Inverse Fast Fourier Transform (IFFT). The work also includes in designing a mapping module, serial to parallel and parallel to serial converter module. The 8 points IFFT / FFT decimation-in-frequency (DIF) with radix-2 algorithm is analyzed in detail to produce a solution that is suitable for FPGA implementation. The FPGA implementation of the project is performed using Very High Speed Integrated Circuit (VHSIC) Hardware Descriptive Language (VHDL). This performance of the coding is analyzed from the result of timing simulation using Xilinx.