Sleep Pass Gate Approach for Static Power Reduction in 8*8 Wallace Multiplier
R. Naveen1, K.Thanushkodi2, C. Saranya3
1R.Naveen, ECE, Info Institute of Engineering, Coimbatore, India.
2K.Thanushkodi, Director, Akshaya College of Engineering and Technology, Coimbatore, India.
3C. Saranya, ECE, Info Institute of Engineering, Coimbatore, India.
Manuscript received on July 17, 2012. | Revised Manuscript received on August 25, 2012. | Manuscript published on August 30, 2012. | PP: 184-188 | Volume-1 Issue-6, August 2012.  | Retrieval Number: F0659081612/2012©BEIESP

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Abstract: As the VLSI technology and supply/threshold voltage continue scaling down, leakage power has become more and more significant in the power dissipation of today’s CMOS circuits. The leakage power dissipation is projected to grow exponentially during the next decade according to the International Technology Roadmap for Semiconductors (ITRS).This affects the portable battery operated devices directly. The multipliers are the main key for designing an energy efficient processor, where the multiplier design decides the digital signal processors efficiency. In this paper, a sleep pass gate method is used to reduce the static power dissipation in 8*8 Wallace tree multiplier architecture which has been designed by using 1-bit full adders. This method uses two complementary sleep transistors connected in parallel forming a gate pass structure. In our proposed leakage reduction method, the actual output logic state is maintained in both active and standby mode of operation. The main objective of our work is to calculate leakage power in 8*8 Wallace tree multiplier with sleep pass gate and it is compared with the 8*8 Wallace tree full adder multiplier. The proposed method reduces upto half of the static power dissipation with lesser area and delay. 
Keywords: Static leakage power, Sleep transistor, Subthreshold leakage, Wallace multiplier, 1- bit full adder.