Design & Simulation of Round Robin Arbiter for NoC Architecture
Suyog K. Dahule1, M. A. Gaikwad2
1Mr. Suyog K.Dahule, M-tech Student Department of Electronics, BDCOE, Sevagram Wardha,(M.H) Wardha ,India.
2Dr. M.A.Gaikwad, Dean (R&D) Department of Electronics, BDCOE, Sevagram Wardha,(M.H)India.
Manuscript received on July 17, 2012. | Revised Manuscript received on August 25, 2012. | Manuscript published on August 30, 2012. | PP: 59-61 | Volume-1 Issue-6, August 2012.  | Retrieval Number: F0605071612/2012©BEIESP

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Abstract: NOC means network on chip is a new method for on chip communication to solve a problem that challenges system on chip. Arbiter is used in network on chip when number of input are requested for same output port , the arbiter has generate the grant signal on the basis of that number of input port getting a priority and the input port transmit a packet to output port. In this paper we have design round robin arbiter for NOC architecture. After design of round robin arbiter we analyze the area and power. 
Keywords: Network on–Chip, Round Robin Arbiter.