A Carry Save Adder Design
S Subha

S Subha, Department of IT and Engineering, SITE, Vellore Institute of Technology, Vellore (Tamil Nadu), India.
Manuscript received on 18 June 2019 | Revised Manuscript received on 25 June 2019 | Manuscript published on 30 June 2019 | PP: 1992-1993 | Volume-8 Issue-5, June 2019 | Retrieval Number: E7650068519/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Full adders add three input numbers and give sum and carryout. The full adders which are faster and energy saving is the need of the hour. Simplifications of the Boolean expressions for addition of two n-bit numbers is one method to achieve this. Other method is to use combinational circuits. Various full adders are proposed in literature. Carry save adder is one of them. They are used in many places. The sum and carry of two 32-bit numbers are calculated in this paper. The sum and carry of inputs is calculated as in carry save adder. The carry is added to the sum based on the values of sum bit resulting in final sum and carry. The proposed logic is simulated using Quarturs 2 toolkit. An improvement in area by 16% with time improvement of 8.56% and comparable power consumption is observed for chosen parameters when compared with model proposed in [5].
Keywords: Area, Boolean logic, Carry save adder, Full adder, Performance

Scope of the Article: Machine Design