Performance Analysis of CMOS Circuits using Shielded Channel Dual Gate Stack Silicon on Nothing Junctionless Transistor
S.C. Wagaj1, S.C. Patil2
1S.C.Wagaj*, Dept. of Electronics & Telecommunication, JSPM’s Rajarshi Shahu College of Engineering, Tathawade, Pune, Savitribai Phule Pune University, Pune ( Maharashtra), India.
2S.C.Patil, Dept. of Electronics & Telecommunication, JSPM’s Rajarshi Shahu College of Engineering, Tathawade, Pune, Savitribai Phule Pune University, Pune ( Maharashtra), India.
Manuscript received on May 02, 2021. Revised Manuscript received on July 13, 2021. Manuscript published on August 30, 2021. | PP: 1-10 | Volume-10 Issue-6, August 2021 | Retrieval Number: 100.1/ijeat.E25760610521 | DOI: 10.35940/ijeat.E2576.0810621
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: In this paper it has been demonstrated that a shielded channel made by varying the side gate length in silicon-on-nothing junctionless transistor not only improves the short channel effect but also improve the performance of CMOS circuits of this device. The proposed device shielded channel dual gate stack silicon on nothing junctionless transistor (SCDGSSONJLT) drain induced barrier lowering (DIBL), cut-off frequency and subthreshold slope are improved by 20%, 39% and 20% respectively over the single material gate silicon on insulator junctionless transistor (SMG SOI JLT). The proposed device CMOS inverter fall time Tf (pS) and noise margin improves by 50% and 10% compare to shielded channel silicon on insulator junctionless transistor (SCSOIJLT). It has been observed that circuit simulation of CMOS inverter, NAND and NOR of proposed device. The static power dissipation in the case of proposed SCDGSSONJLT device are reduced by 45%, 81% and 83% respectively over the SMGSOIJLT. Thus, significant improvement in DIBL, cut-off frequency, propagation delay and static power dissipation at low power supply voltage shows that the proposed device is more suitable for low power CMOS circuits.
Keywords: Shielded channel, junctionless transistor, dual gate stack, silicon on nothing, NAND gate, NOR gate.