Design of Low Power Zigzag 8T SRAM Array with Differential Write Back Scheme
J. Suganthi1, N. Kumaresan2, K. Anbarasi3
1Dr. J. Suganthi, Professor and Head, Department of CSE, Hindusthan College of Engineering and Technology, Coimbatore, India.
2N. Kumaresan, Guide-Senior Lecturer, Department of ECE, Anna University of Technology, Coimbatore, India.
3K. Anbarasi, PG Scholar, Department of ECE, Anna University of Technology, Coimbatore, India.
Manuscript received on May 17, 2012. | Revised Manuscript received on June 14, 2012. | Manuscript published on June 30, 2012. | PP: 524-530 | Volume-1 Issue-5, June 2012. | Retrieval Number: E0463061512/2012©BEIESP

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Abstract: Static random access memory (SRAM) has been widely used as the representative memory for logic LSIs. This is because SRAM array operates fast as logic circuits operate, and consumes a little power at standby mode. array. Therefore, the good design of SRAM cell and SRAM cell array is inevitable to obtain high performance, low power, low cost, and reliable logic LSI. Various kinds of SRAM memory cell has been historically proposed, developed and used. Nanometer SRAM cannot achieve lower VD Dmin due to read-disturb, half-select disturb and write failure. This paper demonstrates quantitative performance advantages of a zigzag 8T-SRAM (Z8T) cell over the decoupled single-ended sensing 8T-SRAM (DS8T) with write-back schemes, which was previously recognized as the most area-efficient cell under large supply voltage variations. In this paper, we propose a new compact z-shape cell layout to prioritize symmetric device placement while providing high area efficiency. 
Keywords: Low supply voltage, SRAM, read disturb, static voltage, SRAM, read disturb, static noise margin, write margin.