FPGA Implementation of Fault Tolerant Adder using Verilog for High Speed VLSI Architectures
Somashekhar1, Vikas Maheshwari2, R. P. Singh3

1Somashekhar*, Department of ECE, SSSUTMS, Sehore(M.P), India.
2Vikas Maheshwari, Associate Professor, Department of ECE, BIET, Hyderabad, India.
3R. P. Singh, Vice-Chancellor & Professor, Department of ECE, SSSUTMS, Sehore (M.P), India.

Manuscript received on March 05, 2020. | Revised Manuscript received on March 16, 2020. | Manuscript published on April 30, 2020. | PP: 549-551 | Volume-9 Issue-4, April 2020. | Retrieval Number: D7062049420/2020©BEIESP | DOI: 10.35940/ijeat.D7062.049420
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: The main objective is to detect and reduce the faults in full adder design using self checking and self repairing adder block. The rate of chip failure is directly proportional to chip density. This fault tolerant adder has high speed (Delay is 6.236ns) & implemented on FPGA Spartan 3 using XC3S50 device. The source code is written in verilog. In this design faults are identified and repaired using self checking and self repairing full adder methodologies.
Keywords: Fault Tolerance, VLSI, Full Adder, Self Checking, FPGA Spartan 3, Self Repairing, Xilinx ISE 14.7, Verilog.