Implementation of High Performance 2D Transform using Area Efficient Even Odd Decomposition Methodology for Future Video Coding
P. Srikanth Reddy1, Y.Viswanadh2, M. Sridhar3
1Mr. P Srikanth Reddy, Assistant Professor, KLEF Deemed To Be University, Bengaluru (Karnataka), India.
2Mr. Y. Viswanadhis, Currently Pursuing, Masters Degree, Department of Electronics and Communication Engineering, VLSI University Gudivada (Andhra Pradesh), India
3Mr. M Sridhar, Masters Degree, VLSI Design KLFI Deemed To Be University. Technology – [VITB], Bhimavaram (Andhra Pradesh), India.
Manuscript received on 18 April 2019 | Revised Manuscript received on 25 April 2019 | Manuscript published on 30 April 2019 | PP: 1800-1805 | Volume-8 Issue-4, April 2019 | Retrieval Number: D6857048419/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Future Video Coding (F.V.C), High Efficiency Video Coding(H.E.V.C) are international image compression standards developed by ITU,ISO,JPEG organizations to produce better compression factor at an expense of high computational complexity. FVC has higher computational complexity and resource utilization compared to HEVC, H.264 standards. FVC utilizes various DCT algorithms for image compression and various IDCT algorithms for image reconstruction. This paper presents an approach for Hardware implementation of 8X8 DCT, IDCT modules in Design1 through HDL (Verilog).Design 1 can generate 64 Transformed Coefficients per cycle. This implementation utilizes hardware resources (multipliers, adders) at higher expense. Inorder to overcome this problem a methodology has been implementedin Design 2 throug heven odd decomposition algorithm. Design 2 can generate 64 transform coefficients per clock cycle with less utilization of multipliers compared to Design 1.Multipliers occupy more area in hardware implementations. This paper mainly focusses to reduce hardware resources as much as possible. To eliminate utilization of multipliers completely a methodology has been proposed in this paper .The proposed methodology has been implemented in Design 3 generates 8 transform coefficients per cycle with complete elimination of multipliers (With Zero (0)multipliers).Design 3 also reduces Four(4) stages of DCT, IDC To perationsto Two(2) stage swhich reduces the number of transform coefficients to be utilized. This modification reduces the adders and shifters count to minimal number. However this implementation produces 64 transform coefficients after 8 clock cycles. Allthe Design sare simulated and synthesized using Xilinx Vivado (2018.1).The result so btaine dare comparedin terms of both simulation and synthesis shows that the Proposed Methodology(Design 3)produces same simulation results as Design 1 and Design 2 with less utilization of hardware resources. This Proposed Hardware Design can be utilized in low power, area efficient FVC modules as it has less number of adders, shifters with complete elimination of multipliers
Keywords: Future Video Coding (F.V.C), High Efficiency Video Coding(H.E.V.C), Discrete Cosine Transform (D.C.T), Inverse Discrete Cosine Transform(I.D.C.T),Even Odd DCT,IDCT Algorithms.
Scope of the Article: High Performance Computing