Design of a 4-bit Arithmetic and Logic Unit using 9T Full Adder with Optimized Area and Speed
Sreeja S Kumar1, Rakesh S2

1Sreeja S Kumar, Department of ECE, Mangalam College of Engineering, Ettumanoor (Kerala), India
2Rakesh S, Department of ECE, Mangalam College of Engineering, Ettumanoor (Kerala), India

Manuscript received on 18 June 2019 | Revised Manuscript received on 25 June 2019 | Manuscript published on 30 June 2019 | PP: 95-98 | Volume-8 Issue-5, June 2019 | Retrieval Number: D6688048419/19©BEIESP
Open Access | Ethics and Policies | Cite | Mendeley | Indexing and Abstracting
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (

Abstract: Arithmetic Logic Unit (ALU) is the most significant unit of any computing system be it microprocessors, embedded structures or any other computational device. This paper presents delay, power, area and energy optimization of a novel 4-bit Arithmetic logic unit created with the help of a newly designed 9T full adder unit and Gate Diffusion Input (GDI) technique. This novel ALU architecture is made by using a full adder which has only 9 transistors and various multiplexers. To analyze the simulations Cadence Virtuoso tool is used. As per simulation results, delay, power, area and total energy of the ALU design is improved. In this proposed design of 4-bit ALU, delay is reduced by 10.17%. power is reduced by 8.05%. PDP is reduced by 18.20% and transistor count is reduced by 17.82 %.
Keywords: Arithmetic Logic Unit (ALU), Cadence Virtuoso tool, Gate Diffusion Input (GDI), Power Delay Product (PDP).

Scope of the Article: Discrete Optimization