A Novel Design of Synchronous Counter for Low Power and High-Speed Applications
Kuruvilla John1, Vinod Kumar R. S.2, Kumar S. S.3
1Kuruvilla John, Research Scholar, Department of Electronics and Communication, Noorul Islam Centre for Higher Education, Thucklay (Tamil Nadu), India, and Assistant Professor, Department of Electronics and Communication, Providence College of Engineering, Chengannur (Kerala), India.
2Vinod Kumar R. S., Professor, Department of Electronics and Communication, Noorul Islam Centre for Higher Education, Thucklay (Tamil Nadu), India.
3Kumar S. S., Associate Professor, Department of Electronics and Instrumentation, Noorul Islam Centre for Higher Education, Thucklay (Tamil Nadu), India.
Manuscript received on 18 April 2019 | Revised Manuscript received on 25 April 2019 | Manuscript published on 30 April 2019 | PP: 779-783 | Volume-8 Issue-4, April 2019 | Retrieval Number: D6280048419/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this paper, a new power efficient and high-speed synchronous up-counter design suitable for low power and high-speed applications is proposed. The clock gating concept embedded in this design reduces unwanted switching activities at sleep/idle mode of operation and thereby reducing dynamic power consumption. The proposed design achieves better speed and power performance by successfully solving the longest discharging path problem and unwanted switching activities. This design can be used in many applications such as memory systems, microcontroller circuits, frequency dividers etc. The simulation results in Cadence Virtuoso based on CMOS 90-nm technology shows that the proposed design features less power dissipation, and better power delay performance (PDP) when compared with conventional designs. The proposed design is having the advantage of 33.50% in power and 30.66% in speed when compared with conventional design. The proposed counter is implemented in Xilinx Spartan-3 FPGA.
Keywords: Clock Gating, Counter, Low Power, Pulse Flip-Flop.
Scope of the Article: Low-power design