Hevc Cabac Encoder/Decoder Ip Designing Using Vivado
Vivek R. Barwat1, Rutesh S. Lonkar2

1Mr. Rutesh S. Lonkar, Assistant Professor, Department of Electronics & Communication Engg., P.I.G.C.E., Nagpur (M.H), India.
2Mr. Vivek R. Barwat, Assistant Professor, Department of Electronics & Communication Engg., P.I.G.C.E., Nagpur (M.H), India.

Manuscript received on 18 April 2019 | Revised Manuscript received on 25 April 2019 | Manuscript published on 30 April 2019 | PP: 630-636 | Volume-8 Issue-4, April 2019 | Retrieval Number: D6244048419/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: For an Ultra HD real time applications, Video compression plays a vital role. There are so many different compressions techniques and algorithm are available now days but HEVC or H.265 is latest updated and most advanced video compression technique. H.265 standard video codec is also known as High Efficiency Video Codec (HE-VC). Now days, It becomes one of the most important and favorable consumer application platforms than that of other video codecs such as Advanced Video Codec. HEVC can support upto 120fps for Ultra High Definition pictures. H.265 has adopted some advanced and highly efficient methodologies such as Inter and Intra Prediction, SAO filter and CABAC (Context Based Arithmetic Coding) encoder. CABAC encoding is totally based on entropy based encoding technique. Here, we proposed IP designing of HEVC CABAC encoder and its hardware and software implementation. Initially, we are using MATLAB Simulink tool for implementation of control of encoding process. Lateron, we will try to reduce resources and storage hardware implementation cost by using several arithmetic encoding methods at lower level coding blocks and also, it introduces pipeline structure within it. To achieve desired tradeoff in between the resources cost and the throughput, we proposed the architecture with 5 bypassed and 2 regular bins per cycle process that can be demonstrated through our FPGA synthesis results
Keywords: CABAC Encoder, HEVC Video Codec

Scope of the Article: IoT Application and Communication Protocol