Design of Low Power 8T SRAM Array With Enhanced RNM
M. Muzammil Khaleeq1, Kartik Penshanwar2, Ananiah Durai S3, Ravi V4

1M. Muzammil Khaleeq, B.E degree in Electronics and Communication from REVA ITM, Bangalore and is presently pursuing M.Tech in VLSI Design from VIT, Chennai (Tamil Nadu), India.
2Kartik Penshanwar, M.Tech (VLSI Design) from VIT Chennai . He completed B.E in Electronics and Telecommunication form Pune University, Pune (M.H), India.
3Ananiah Durai S, PhD in “Electronic Integrated design” from Massey University, Auckland, New Zealand.
4Ravi V, B.E from University of Madras and M.E from College of Engineering Guindy, Anna University and pursuing his PhD at VIT Chennai (Tamil Nadu), India.

Manuscript received on 18 April 2019 | Revised Manuscript received on 25 April 2019 | Manuscript published on 30 April 2019 | PP: 553-557 | Volume-8 Issue-4, April 2019 | Retrieval Number: D6187048419/19©BEIESP
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Abstract: The paper discusses about the power reduction techniques in a memory cell. Two commonly used SRAM cells, 6T and 8T SRAM are compared in terms of their stability and power gating and MTCMOS technique is implemented to observe power reduction. 8T SRAM cell proves to be more reliable and stable as this has decoupled read and write control paths. The 8T SRAM cell is optimized for better RNM and an array of 4×8 bit cell is constructed with proposed 8T cell. The array with the MTCMOS technique used in the decoder proves 6.9 % power reduction than the circuit without the MTCMOS technique. The 32-bit cell array is constructed with gpdk 180 and consists of 8 write driver circuit, 8 precharge circuit and 8 sense amplifier along with 2:4 decoder and 32 SRAM cells.
Keywords: Low Power, RNM, SRAM, Array, 6T, 8T

Scope of the Article: Low-Power Design