Performance Comparison of JL Fin FETs with Variability in Fin Structure and Shape
Ayoob Khan T. E1, Shahna M2, Shahul Hameed T. A.3

1Ayoob Khan T E, Electronics and Communication Engineering, College of Engineering Chengannur (Chengannur), India.
2Shahna M, Electronics and Communication Engineering, College of Engineering Chengannur (Chengannur), India.
3Shahul Hameed T A, Electronics and Communication Engineering, TKM College of Engineering, Kollam (Kerala), India.

Manuscript received on 18 April 2018 | Revised Manuscript received on 27 April 2018 | Manuscript published on 30 April 2018 | PP: 103-106 | Volume-7 Issue-4, April 2018 | Retrieval Number: D5359047418/18©BEIESP
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Abstract: To avoid the scaling challenges of CMOS the Junctionless transistors (JLT) has recently been proposed. Unlike conventional transistors, JLT have no junctions i.e source/drain /channel regions are uniformly doped with same species and that is the main advantage of JLT. In this study, the impact of work function variation(WFV), spacer dielectric, material engineering on the performance of conventional P channel Junctionless FinFET is analyzed. Trapezoidal and Multifin structures of JL FinFETs are proposed and same impact is considered under similar conditions at supply voltage -0.9 V. All studies are carried out using Silvaco Atlas TCAD tool. The basic performance parameters under consideration are off current ,VTH, SS & ION/IOFF ratio and observed characteristics fluctuations on the devices. The proposed architecture shows better short channel characteristics and also provides better ION/IOFF ratio compared to conventional JL FinFET.
Keywords: JL Fin FET, Spacer Dielectric, Sub threshold Slope, Work Function Variation

Scope of the Article: Function Virtualization