Design SSTL based Arithmetic Logic Unit for Internet of Things Based Processor
Chandrashekhar Patel1, Abhay Saxena2
1Mr. Chandrashekhar Patel*, Research Scholar, Dev Sanskriti Vishwavidyalaya, Haridwar (Uttarakhand), India.
2Prof. Abhay Saxena, Dean (School of Technology, Management & Communication), Dev Sanskriti Vishwavidyalaya, Haridwar (Uttarakhand), India.
Manuscript received on 22 March 2022 | Revised Manuscript received on 20 April 2022 | Manuscript published on 30 April 2022 | PP: 142-145 | Volume-11 Issue-4, April 2022. | Retrieval Number: 100.1/ijeat.D34770411422 | DOI: 10.35940/ijeat.D3477.0411422
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Now days in area of computer science Green computing is creating revolution by bringing some new digital component with less power consumption. Our research work is created on this idea. In this paper our objective is to come up with High Performance ALU design for IOT based processor by reducing the power consumption. For calculating total power consumption of FPGA based ALU we used five different voltage (0.95,1.0,1.05,1.10,1.15,1.20) and calculated IOs, Leakage power at four different IOs standard (SSTL18_II, SSTL15, SSTL135, SSTL15_R). In experiment we found the best result with SSTL15_R IO standard. We think that the application of this design will definitely help to design in futuristic IOT based processor development.
Keywords: ALU, SSTL, Verilog, RTL, SSTL18_II, SSTL15, SSTL135, SSTL15_R
Scope of the Article: Internet of Things