A 2.8 GHz Low Power High Tuning Voltage Controlled Ring Oscillator
M. Sai Sarath Kumar1, M. Aarthy2
1M. Sai Sarath Kumar,  M. Tech VLSI Design, VIT University, Vellore, India.
2PM. Aarthy,  Department of Engineering, SENSE, VIT University, Vellore, India.
Manuscript received on March 25, 2014. | Revised Manuscript received on April 13, 2014. | Manuscript published on April 30, 2014. | PP: 145-147 | Volume-3, Issue-4, April 2014. | Retrieval Number:  D2942043414/2013©BEIESP

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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: This work describes a two-stage CMOS Voltage Ring Oscillator (VCRO) using differential delay cells are analyzed. The main aim of the paper is to increase the tuning range of the circuit and obtain a good phase noise at the cost of design complexity and power consumption. Two-stage VCRO implemented in 90 nm Technology realizes a tuning range of 53.40% and a phase noise of -156.328 dBc, Hz for a power consumption of 9.85mW. The phase noise of the VCRO is bettered by cascading more number of stages to trade off power consumption A four-stage VCRO is implemented and achieved a tuning range of 62.15% and a phase noise of -116.608 dBc, Hz. However the power consumption of the circuit increased to 16.45mW.
Keywords: Voltage Ring Oscillator, Phase Noise, Tuning Range.