An Architecture for Low Power Binary Motion Estimation Architecture
V.Prathap Reddy1, MahendraVucha2
1V.Prathap Reddy, Department of Electronics & Communication Engineering, KL University, Vijayawada (A.P.), India.
2Mahendra Vucha, Department of Electronics & Communication Engineering, KL University, Vijayawada (A.P.), India.
Manuscript received on March 22, 2013. | Revised Manuscript received on April 16, 2013. | Manuscript published on April 30, 2013. | PP: 351-355 | Volume-2, Issue-4, April 2013. | Retrieval Number: D1558042413/2013©BEIESP

Open Access | Ethics and Policies | Cite
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: As technology increases, there is a need of fast computing systems to enhance multimedia applications. In this paper, architecture is designed for fixed block size and Variable Block Size (VBS) Motion Estimation Algorithm (MEA). The proposed architectures perform Motion Estimation (ME) by applying Diamond search (DS) algorithm on 1-Bit Transform (1- BT) image frames. The DS based 1-BT ME architecture reduces the minimum clock frequency required and overall power consumption compared with other ME architectures. So, the proposed architectures can be suitable for low power portable video application. The behavior of proposed architecture described in Verilog HDL and functional verification is done using Modelism simulation tool.
Keywords: HDL, VBS, MEA.