A Low Power Shift Add Multiplier for Lifting Based Dwt using Kogge Stone Adder
A. Akilandeswari1, Annie Grace Vimala2, D.Sungeetha3

1Dr. A. Akilandeswari*, Associate Professor, Department of Electronics and Communication Engineering ,St.Joseph’s Institute of Technology, Chennai, India.
2Dr. Annie Grace Vimala, Department of Electronics and Communication Engineering, B.S. Abdur Rahman University.
3Dr. D. Sungeetha, Department of Electronics and Communication Engineering, Sathyabama Institute of Science and Technology, Chennai, India. 

Manuscript received on March 30, 2020. | Revised Manuscript received on April 05, 2020. | Manuscript published on April 30, 2020. | PP: 1080-1086 | Volume-9 Issue-4, April 2020. | Retrieval Number: C6211029320/2020©BEIESP | DOI: 10.35940/ijeat.C6211.029320
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: The most common technique used for image processing applications is ‘The wavelet transformation’. The Discrete Wavelet Transform (DWT) keeps the time as well as frequency information depend on a multi resolution analysis structure, where the other classical transforms like Fast Fourier Transform (FFT), Discrete Cosine Transform (DCT) will not do that. Because of this feature, the quality of the repaired image is improved when comparing to the other transforms. To implement the DWT on a real time codec, a fast device needs to be targeted. While comparing with the other implementation such as PCs, ARM processors, DSPs etc, Field Programmable Gate Array (FPGA) implementation of DWT had better processing speed and costs were vey less. A Fast Architecture based DWT using Kogge Stone Adder is proposed in this paper where the coefficients of lifting scheme are calculated by using Shift adder and Kogge Stone Adder where other techniques used multiplier. The most important intention of the suggested technique is to use minimum calculation and limited memory. The simulation of the suggested design is dole out on the Xilinx 14.1 style tool and also the performance is evaluated and compared with the present architectures.
Keywords: Kogge Stone Adder, Lifting Scheme, Shift Adder, Multiplier, DWT