An Efficient Architecture of Vedic Multiplier using FinFet Based Pass Transistor Logic
B. Paulchamy1, K. Kalpana2, J. Jaya3

1Dr. B. Paulchamy*, Professor and Head, Department of ECE, Hindusthan Institute of Technology, Coimbatore.
2K. Kalpana, Research Scholar, Department of ECE, Hindusthan Institute of Technology, Coimbatore.
3Dr. J. Jay, Principal, Akshaya College of Engineering and Technology, Coimbatore.
Manuscript received on January 26, 2020. | Revised Manuscript received on February 05, 2020. | Manuscript published on February 30, 2020. | PP: 2605-2611 | Volume-9 Issue-3, February 2020. | Retrieval Number:  C5311029320/2020©BEIESP | DOI: 10.35940/ijeat.C5311.029320
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Abstract: Multiplies is an important component in Digital Signal Processing (DSP) and communication systems. It is utilized in signal and image processing applications including convolution, Fast Fourier Transform (FFT) and correlation. Therefore, it is necessary to develop a multiplier with power efficient and speed to reduce the cost of the system. Vedic multiplier has been introduced to solve the problems of existing multiplier. It is based on 16 algorithms. These algorithms use algebra, arithmetic operations and geometry. Urdhva Tiryabhyam is widely employed formula which provides high speed and efficient. Vedic multiplies generates partial sums and products in single step. It has been designed using pass transistor logic which reduces the number of components utilized to build logic gates by removing unwanted transistors. This paper design a vedic multiplier with FinFET based pass transistor logic. The developed multiplies provides better performance and suitable for high speed applications. 2×2 and 4×4 vedic multipliers are developed and executed 180nm approach with Tanner EDA Tool 3.0.
Keywords: Vedic Multiplier, FinFET based Pass Transistor, High performance, Low power optimized circuit.