Physical Design Implementation of Processor Torpedo at Different OCV Scenarios -40, 25, 125 Degree Celsius of an ASIC Design Chip
Tauseef Amin Azmi
Tauseef Amin Azmi. VLSI Research Academy, RV-VLSI Design Centre Jayanagar, Bangalore, Karnataka, India.
Manuscript received on January 25, 2014. | Revised Manuscript received on February 13, 2014. | Manuscript published on February 28, 2014. | PP: 257-259  | Volume-3, Issue-3, February 2014. | Retrieval Number:  C2692023314/2013©BEIESP

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Abstract: This Paper basically studies the physical design implementation of torpedo processor which incorporates 32 macros in overall and 43000 cell instances .We had 5 clocks ,3 propagated and 2 generated clock in a die size of 5.9 mm square which operated at a frequency of 400 megahertz having a supply voltage of 1.8 volts .The technology which we worked was 180 nm technology and working on the IC Compiler tool from synopsys and then moving on to static timing analysis part on the Prime time tool from synopsys and then further moving on to drc/lvs checking on the tool Calibre from mentor graphics. The foundry which supplied us the 180 nm technology documents was Jazz semiconductors INC. The earlier work on this project that were carried out were at different scenarios and hence the results were with different optimization ,here in our study we had made a comprehensive and mature step to achieve the maximum optimization of the placement of the standard cells and therefore in our effort we had chosen the three scenarios for our thesis which were three operating conditions :function minimum, function maximum , CTS maximum. The temperature that we worked on the physical design implementation of this block level subsystem were -40 degree celcius , 25 degree celcius ,125 degree celcius. The three scenarios supply voltages were 1.65 volts ,1.8 volts and 1.9 volts respectively and the power dissipation was 300 milliwatts with a pre cts derate of 15 % and post cts derate of also 15% respectively. The thesis was not so easy to carry out as we had several problems occurring at every step like the IR DROP was exceeding the limit which was provided as 5% of the total VDD+VSS supposed to be within 90 mv also errors from routing congestion and DRC errors were prompt.
Keywords: ASIC Design, OCV,VLSI, Physical design, Scenarios.