Low Voltage, High Gain CMOS Op Amp Using Nested Transconductance Compensation Capacitance
Hardik Patel1, Rajnikant Son2
1Hardik Patel, Electronic & communication, VLSI System Design, College LCIT, Bhandu and Gujarat Technological University, Ahmedabad, India.
2Rajnikant Soni, Electronics and Communication, Gujarat Technological University, Mehsana, India.
Manuscript received on January 22, 2013. | Revised Manuscript received on February 14, 2013. | Manuscript published on February 28, 2013. | PP: 387-390 | Volume-2 Issue-3, February 2013.  | Retrieval Number:  C1149022313/2013©BEIESP

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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: An analytic design guide was formulated for the design of 3-stage CMOS OP amp with the nested Gm-C(NGCC) frequency compensation. The proposed design guide generates straight-forwardly the design parameters such as the W/L ratio and current of each transistor from the given design specifications, such as, gain-bandwidth, phase margin, the ratio of compensation capacitance to load capacitance. The applications of this design guide to the 10pF load capacitances, shows that the designed OP amp work with a reasonable performance in both cases, for the range of compensation capacitance from 10% to 100% of load capacitance.
Keywords: Low voltage OP amp, design guide, frequency compensation, nested Gm-C.