Design Low Power 32-Bit Barrel Shifter Using Efficient Charge Recovery Logic
Shweta Chawla1, Ramanand Harijan2, Harpal singh3
1Shweta Chawla, Department of ECE & EEE, BM Group of Institution, Gurgaon, India.
2Ramanand Harijan, Department of ECE & EEE, BM Group of Institution, Gurgaon, India.
3Harpal Singh, Department of ECE, Sgtiet, Gurgaon, India.
Manuscript received on January 12, 2013. | Revised Manuscript received on February 02. 2013 | Manuscript published on February 28, 2013. | PP: 140-145 | Volume-2 Issue-3, February 2013. | Retrieval Number: C1049022313/2013©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Today power dissipation has become the main concern as the circuit size become larger and larger. Especially in this paper we presented the reduction of the power dissipation which shows an increasing growth as the technology is scaled down. Various theories have been formulated regarding this problem. Out of which Adiabatic Logic is gaining much attention because of its exemplary results. By adiabatic technique, power dissipation in transistors can be minimized as well as energy stored in load capacitance can be reused instead of dissipation as heat. In these circuits we can reduce the energy dissipation during switching process as well as reuse the energy from the load capacitance by making a feedback path from load capacitance to the supply.In this paper we first study of various adiabatic techniques and will lay emphasis on one of its widely used technique called the Efficient Charge Recovery Logic (ECRL). We will study how ECRL technique is better than the rest and how circuits are implemented using it. Using this technology we will design a 32 bit barrel shifter and perform various tests on the circuit. We will also compare the results of this adiabatic technology with the normal CMOS technology and show the drastic reduction in power dissipation. All the design structures based on Adiabatic Switching Logic are designed and simulated using standard TSMC 0.18 μm CMOS technology and 5 V voltage supply at an operating temperature of 27º C. Mentor Graphics Corporation based tool known as IC Design Architect have been used for all the design and analysis.
Keywords: Low power, Adiabatic, ECRL, Fully Adiabatic, Partially Adiabatic Circuit (Quasi),Barrel shifter, Multiplexor.