Design, Implementation and Verification of Image Compression in High Speed DWT Algorithm for VLSI Applications
M.K. Deepa1, Amay Shiva Naik2, Rashmi Priyadarshini3
1M.K. Deepa, Department of ECE, Reva University, Bangalore (Karnataka), India.
2Amay Shiva Naik, Department of ECE, Reva University, Bangalore (Karnataka), India.
3Rashmi Priyadarshini, Department of ECE, Reva University, Bangalore (Karnataka), India.
Manuscript received on 25 May 2019 | Revised Manuscript received on 03 June 2019 | Manuscript Published on 22 June 2019 | PP: 49-53 | Volume-8 Issue-3S, February 2019 | Retrieval Number: C10110283S19/19©BEIESP
Open Access | Editorial and Publishing Policies | Cite | Mendeley | Indexing and Abstracting
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (

Abstract: The proposed DWT architecture for Image Compression targets the high-Speed processing improvement of DWT algorithm as compared to the existing architectures. It mainly includes line buffers, PIPO and lifting blocks. The methodology of using lifting scheme was to make architecture in a non-separable fashion and also to compute DWT algorithm at different resolutions. The RTL design will be coded via Verilog & synthesized using Xilinx ISE and vivardo tools, targeted on Spartan-6. The proposed architecture is scalable which can be parameterized for any size N(32,64,128,…..512). By the performance observation in the proposed architecture in terms of operating frequency for 128X128 image is 322.316 MHz implemented on spartan6 (xc6vhx565t-2ff1923) of FPGA board whereas it was seen in other architectures the maximum operating frequency was 254 MHz.
Keywords: Proposed Architecture for DWT Algorithm, 2-D Image Compression, Verilog, Questa Sim, Xilinx ISE.
Scope of the Article: High Speed Networks