Design and analysis of 32-bit CPU based on MIPS
Anil Kumar Vajja1, B.Bhaskar Rao2
1Anil Kumar Vajja, ECE, St.Teresa Institute of Engineering and Technology, Visakhapatnam, India.
2B.Bhaskar Rao, HOD , ECE Department ,St.Teressa Institute of Engineering and Technology. Vizianagaram, India.
Manuscript received on January 22, 2012. | Revised Manuscript received on February 19, 2012. | Manuscript published on February 29, 2012. | PP: 161-166 | Volume-1 Issue-3, February 2012. | Retrieval Number: C0214021312/2011©BEIESP

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Abstract: In this paper, we have studied Microcomputer with out interlocked pipeline stages instruction format instruction data path decoder module function and design theory basend on RISC CPUT instruction set. We have also designed instruction fetch(IF) module of 32-bit CPU based on RISC CPU instruction set. Function of IF module mainly includes fetch instruction and latch module address arithmetic module check validity of instruction module synchronous control module. Function of IF modules are implemented by pipeline and simulated successfully on Xilinx Spartan 3E fpga device.
Keywords: MIPS, Data Flow, Data Path, Pipeline