A Reduced Clock Power Flip-Flop for Sequential Circuits
G. Bhala Bharath1, R. Ramana Reddy2
1G. Bala Bharat,  M. Tech Degree in VLSI Design in MVGR College, JNTU University Kakinada, Vizainagaram, India.
2Dr. R Ramana Reddy, Professor & Head, Department of ECE in MVGR College of Engineering, Vizianagaram, India.
Manuscript received on November 25, 2014. | Revised Manuscript received on December 09, 2014. | Manuscript published on December 30, 2014. | PP: 168-172 | Volume-4 Issue-2, December 2014. | Retrieval Number:  B3657124214/2013©BEIESP

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Abstract: In most Very Large Scale Integration digital circuits, clock system is one of the major power consuming component. It consumes around 40% of the total system power. There is need to reduce the power consumption because power budget is severely limited on portable digital circuits. In this paper, a new Low Power Clocked Pass Transistor Flip-Flop is proposed, which will considerably reduce the number of transistors in the discharging path and also reduces the capacity of the clock load by minimizing number of clocked transistors leading to reduction in clocking power which will improve the overall power consumption. Proposed reduced clock power flip flop is compared with conventional flip flops and Parallel In Parallel Out shift register is designed using this proposed flip-flop. Simulations are done using Microwind & Tanner software tools.
Keywords: Flip-flop, Low Power Clocking System, Microwind, Pass transistors, Shift register, Tanner.