Design and Implementation of 256 Bit Modified Square Root Carry Select Adder for Area and Delay Reduction
Agnes Shiny Rachel1, Rajakumar.G2
1Agnes Shiny Rachel, Assistant Professor (ECE) in Sri Krishna College of Technology,Coimbatore.
2Rajakumar.G, Professor (ECE) in Francis Xavier Engineering College,Tirunelveli.
Manuscript received on November 25, 2019. | Revised Manuscript received on December 08, 2019. | Manuscript published on December 30, 2019. | PP: 407-410 | Volume-9 Issue-2, December, 2019. | Retrieval Number: B3271129219/2019©BEIESP | DOI: 10.35940/ijeat.B3271.129219
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper models the behaviour of modified Square Root Carry Select Adder and goes deep to investigate on its scope of reducing area and delay. This helps to overcome the drawback of conventional RCA by performing operations simultaneously for both Cin = 0 and Cin = 1, and the output is multiplexed to obtain the desired response. The work explores opportunities to reduce the area with introduction of BEC logic instead of second block RCA. The implementation of a 4 bit MCSLA and its capability of extending its word size to 8, 16, 32, 64, 128 and 256 bits are presented. The experimental result helps to verify the effectiveness of the approach. This provides understanding on how the reduction of area can bring vital improvements in Very Large Scale Integration.
Keywords: RCA, BEC, MCSLA, Delay, Area