Test Escape Study IN IC Manufacturing
Sarath Chand.L1, D.A.R.Nikhilesh2, Suresh Angadi3
1Sarath Chand.L, Department of ECE Assistant Professor, Vaddeswaram, Vijayawada, (Andhra Pradesh), India.
2D.A.R.Nikhilesh, Department of ECE Assistant Professor, Vaddeswaram, Vijayawada, (Andhra Pradesh), India.
3Suresh Angadi, Department of ECE Assistant Professor, Vaddeswaram, Vijayawada, (Andhra Pradesh), India.
Manuscript received on November 24, 2012. | Revised Manuscript received on December 13, 2012. | Manuscript published on December 30, 2012. | PP: 193-194 | Volume-2, Issue-2, December 2012. | Retrieval Number: B0879112212 /2012©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The invention of IC technology has paved way for modern application and has miniaturized devices with low power consumption and high operational capabilities. India though is a developing country it has very few industries in the field of integrated circuits. SPEL semiconductor is the only organization in India with facilities of IC assembly and testing. The steps involved in the organization make sure that high yield is produced. The raw material passes through a series of steps like assembly and testing before being dispatched to the customer. There are many other supporting facilities which help the main operations of SPEL. Quality of the material is maintained high with “RIGHT THE FIRST TIME” as the motive. SPEL aims to become a natural destination for assembly processes. The hierarchy in SPEL is arranged so as the processes happens in a time effective manner. OJET, which is the main motive of this program aims at making a student highly salable finished product equivalent to that of an IC assembled in SPEL. Improving efficiency of existing material can be obtained only if the existing workforce spends their time on value added services. For this the concept of motion study is utilized by whichwe can determine the operator efficiency and can use the data to produce rational and reasonable results. The status of machines are obtained to find out the amount of production and the wastage in resources.TR in pocket fail check has also been done to verify the procedure employed by operators in case of TR in pocket fail error. LOT PROCESSING involves following a lot from the time of entry to testing to the stage of getting reeled. For gravity handlers the times taken for each steps in processing of a lot are calculated and time periods of each are compared and top errors are tackled. For SRM HANDLERS the frequencies of errors are measured and the errors with high frequencies are minimized. SETUP STUDY has also been done as part of the program in which the time taken for different steps in setup is calculated and the non-value adding time is reduced. By doing setup study and lot processing the production rate can be improved by diminishing time wasters and reducing high frequency errors. However all said it would a futile attempt not to provide any solutions to the data analyzed by the above method. With respect to the company’s functioning, feasibility and resources available solutions have been provided to the problems that were identified. The production is expected to raise with implementation of these solutions. There is also a great deal of experience and wisdom that has been culminated during these four months.
Keywords: LOT PROCESSING, SETUP STUDY, SPEL, IC, SRM HANDLERS.