Probabilistic Analytical Framework to Minimize Expected Leakage by Employing A Dual Vth Design Technique
Rashmi Bahal1, Shyam Akashe2 , Arun Agrawal3
1Rashmi Bahal, M.Tech VLSI Student, Electronics Department, Gwalior (M.P) India.
2Shyam Akashe.,Associate Professor, Electronics Department, Gwalior (M.P) India.
3Arun Agrawal, Assistant Professor, Electronics Department, Gwalior (M.P) India.
Manuscript received on November 28, 2011. | Revised Manuscript received on December 19, 2011. | Manuscript published on December 30, 2011. | PP: 99-105  | Volume-1 Issue-2, December 2011. | Retrieval Number: B0155121211/2011©BEIESP

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Abstract: The growing demand in the multimedia rich applications are motivating the low-power and high-speed circuit designer to work more closely towards the design issues arising from the design trade-offs in power and speed. This paper targets the modeling and simulation of leakage currents and its minimization approach by Dual Vt approach. We consider the optimal selection of Vth under a statistical model of threshold variation. Probabilistic analytical models are introduced to account for the impact of Vth uncertainty on leakage power and timing slack. Using this model, we show that the non-probabilistic analysis significantly underestimates the leakage power.
Keywords: Dual Vth ,high-speed, leakage current, , Probabilistic analytical models.