A Report on Differential Delay Analysis for Bus Codec
Latika Pinjarkar1, Kamal Mehta2
1Latika Pinjarkar, Associate Professor, Department of IT, SSCET, Junwani  Bhilai (CG),India.
2Kamal Mehta, HoD, Department of CSE, SSCET, Junwani, Bhilai (CG),India.

Manuscript received on November 14, 2011. | Revised Manuscript received on December 22, 2011. | Manuscript published on December 30, 2011. | PP: 34-36  | Volume-1 Issue-2, December 2011. | Retrieval Number: B0128111111 /2011©BEIESP

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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Design of portable consumer electronic devices such as mobile phones, video game and other embedded systems are increasingly demanding low power consumption to maximize the battery life, reduce weight and increase reliability. These types of power sensitive devices are equipped with microprocessors as the processing elements and memories as the storage units. With current complementary metal oxide semiconductor technology a large portion of power consumption is consumed as dynamic power. Bus encoding techniques for low power consumption have been studied in the last couple of decades. Which includes Frequent Value Encoding method, Bus Invert Coding method and Gray Encoding Method .But these techniques could not become the part of Computer architecture because data profile based analysis was not done and delay based analysis was not done. So these techniques are not compatible to incorporate in the computer architecture. The contribution of our work is to design a methodology for optimizing CMOS circuits to incorporate the bus codec techniques by doing the delay based analysis.
Keywords: Bus encoding, Differential Delay, Glitches, Inertial Delay.