Design 10-Transistor (10t) Sram using Finfet Technology
Jyoti Verma1, Abhiruchi Passi2, Savita Sindhu3, S.Gayathiri4

1Jyoti Verma*, ECE Dept. MRIIRS, Faridabad, India.
2Abhiruchi Passi, ECE Dept.  MRIIRS, Faridabad, India.
3Savita Sindhu, CSE Dept. MRIIRS, Faridabad, India.
4S.Gayathiri, MRIIRS, Faridabad, India,
Manuscript received on September 22, 2019. | Revised Manuscript received on October 05, 2019. | Manuscript published on October 30, 2019. | PP: 566-572 | Volume-9 Issue-1, October 2019 | Retrieval Number: A9690109119/2019©BEIESP | DOI: 10.35940/ijeat.A9690.109119
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Abstract: This paper discuss designing of low power, high-speed 10-Transistor (10T) SRAM and analysis of SRAM cell in Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and Fin FET technology. MOSFET is used widely in many areas, but below 40 nm technology control of channel region becomes extremely difficult. So there is a necessity for new innovative technology which allows designers to design below 40nm technology and can offer excellent control over gate thus reducing short channel effects. The designing of SRAM is analyzed using TANNER EDA tool and Microwind.
Keywords: VLSI, Micro Wind, Tanner EDA, VDD, SRAM, Delay, Power, Temperature.