Eight directional Smart Reconfigurable Router Design for Network on Chip (Noc)
Himani Mittal Gupta1, Yogendera Kumar2

1Himani Mittal Gupta,  Associate Professor, E&C, R.K.G.I.T, Ghaziabad.
2Yogendera Kumar, Professor, School of Electrical Electronics and Communication Engineering Galgotia University, Greater Noida, (U.P), India.
Manuscript received on September 13, 2019. | Revised Manuscript received on October 05, 2019. | Manuscript published on October 30, 2019. | PP: 556-559 | Volume-9 Issue-1, October 2019 | Retrieval Number: A9677109119/2019©BEIESP | DOI: 10.35940/ijeat.A9677.109119
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Designing N.O.C routers are based on performance parameters like power dissipation , energy , latency[2]. These performance are usually defined during design time. Taking under consideration all parameters as buffer size while designing lead to higher side of power dissipation and higher latency . Large size buffers lead to good performance but at the same time cause excess power dissipation. In this paper our aim is to design a router which supports heterogeneous data.
Keywords: Network on Chip (NoC) Heterogeneous Reconfigurable Router, Buffer, Latency, Power dissipation, Register Transfer Level (RTL) Design, Low Power, Low Area, Throughput, Latency, Critical time path.