Performance Evaluation of Approximate Adders: Case Study
Yamini Devi Ykuntam1, Bujjibabu Penumutchi2, Bala Srinivas Peteti3, Satyanarayana Vella4
1Yamini Devi Ykuntam, Department of Electronics and Communication Engineering, Aditya Engineering College, Surampalem (A.P), India.
2Bujjibabu Penumutchi, Department of Electronics and Communication Engineering, Aditya Engineering College, Surampalem, (A.P), India.
3Bala Srinivas Peteti, Department of Electronics and Communication Engineering, Aditya Engineering College, Surampalem, (A.P), India.
4Satyanarayana Vella, Department of Electronics and Communication Engineering, Aditya Engineering College, Surampalem (A.P), India.
Manuscript received on 21 September 2022 | Revised Manuscript received on 28 September 2022 | Manuscript Accepted on 15 October 2022 | Manuscript published on 30 October 2022 | PP: 68-75 | Volume-12 Issue-1, October 2022 | Retrieval Number: 100.1/ijeat.A38361012122 | DOI: 10.35940/ijeat.A3836.1012122
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: A computing device designed to carry out a variety of arithmetic computations. The adder circuit, whose operation must be quick with a small area of occupancy, performs the addition, which is a necessary operation in many other mathematical operations including subtraction, multiplication, and division. There is a mandate for an adder circuit with minimal power consumption, minimal delay, and minimal size in various real-time applications such as processing of signals, pictures & video, VLSI data pathways, processors, neural networks, and many more. There is a new class of adders called approximation adders that operate inaccurately but with favorable area, speed, and power consumption. Since their output is inaccurate, the other names for approximate adders are imprecise adders. This set of adders operates at a high speed thanks to a circuit critical path design that uses fewer components. Additionally, compared to precise adders, the approximate adder circuit has a relatively low component count, resulting in a small footprint and circuits that use less energy. There are different ways to create approximate adders. The area can be predicted by counting the number of circuit components that are present. By examining a number of the critical path’s components, delay can be predicted. Several errors that appear in the output of the particular circuit can be used to calculate the accuracy percentage. This review compares approximate adders from four different categories across the board in terms of design constraints and makes note of the differences between each adder.
Keywords: Approximate Adder, Approximate Mirror Adder (AMA), Approximate Adders using XOR/XNOR gates (AXA), Accuracy, Approximate Adder Designs (APAD).
Scope of the Article: Cloud Computing