Area Efficient Higher Order FIR Filter Design using Improved Distributed Arithmetic with Look up Tables
R. Santosh1, K.V. Lalitha Bhavani2
1R. Santosh, M. Tech  Department of ECE, AITAM , Tekkali, India.
2K. V. Lalitha Bhavani,  Assoc. Prof. Department of ECE, Tekkali, India.
Manuscript received on September 29, 2014. | Revised Manuscript received on October 15, 2014. | Manuscript published on October 30, 2014. | PP: 213-216  | Volume-4 Issue-1, October 2014. | Retrieval Number:  A3533104114/2013©BEIESP

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Abstract: This paper describes the design and implementation of highly efficient LUT based circuit for the implementation of FIR filter using Distributed arithmetic algorithm. It is a multiplier less fir filter designed and designed based on distributed arithmetic algorithm. The DA based technique consists of Look Up Table (LUT), shift registers and scaling accumulator. Analysis on the performance of filter order with partition on different address length of partial tables are done using Xilinx 12.1 synthesis tool. The proposed architecture provides an efficient area-time-power implementation which improves latency and less area-delay complexity through pipelining technique when compared with existing structures for FIR Filter.
Keywords: Distributed Arithmetic (DA), FIR filter, Look up table (LUT), FPGA.